CS5535 datasheet(373/555 Pages) NSC

373 / 555 page

Revision 0.8

373

www.national.com

UART/IR Controller Register Descriptions (Continued)

5.12.3.4

Link Control/Bank Select Registers

These registers share the same address.

The Link Control Register (LCR) selects the communication format for data transfers in UART, SIR and Sharp-IR modes.

The Bank Select Register (BSR) is used to select the register bank to be accessed next.

Reading the register at this address location returns the content of the BSR. The content of LCR can be read from the

Shadow of Link Control register (SH_LCR) in Bank 3, I/O Offset 01h (see Section 5.12.6.2 on page 388). During a write

operation to this register at this address location, setting of Bank Select Enable (BKSE, bit 7) determines the register to be

accessed, as follows:

• If bit 7 is 0, both LCR and BSR are written into.

• If bit 7 is 1, only BSR is written into and LCR remains unchanged. This prevents the communication format from being

spuriously affected when a bank other than Bank 0 or 1 is accessed.

Link Control Register (LCR)

Bits 6 to 0 are only effective in UART, Sharp-IR and SIR modes. They are ignored in CEIR mode.

I/O Offset

03h

Type

Reset Value

00h

LCR Register Map

BKSE

SBRK

STKP

EPS

PEN

STB

WLS[1:0]

LCR Bit Descriptions

Bit

Name

Description

BKSE

Bank Select Enable.

0: Register functions as the Link Control register (LCR).

1: Register functions as the Bank Select register (BSR).

SBRK

Set Break. Enables or disables a break. During the break, the transmitter can be used as a

character timer to accurately establish the break duration. This bit acts only on the trans-

mitter front end and has no effect on the rest of the transmitter logic. When set to 1, the fol-

lowing occurs:

— If UART mode is selected, the UART[x]_TX pin is forced to a logic 0 state.

— If SIR mode is selected, pulses are issued continuously on the UART[x]_IR_TX pin.

— If Sharp-IR mode is selected and internal modulation is enabled, pulses are issued

continuously on the UART[x]_IR_TX pin.

— If Sharp-IR mode is selected and internal modulation is disabled, the

UART[x]_IR_TX pin is forced to a logic 1 state.

To avoid transmission of erroneous characters as a result of the break, use the following

procedure:

— Wait for the transmitter to be empty (TXEMP = 1).

— Set SBRK to 1.

— Wait for the transmitter to be empty, and clear SBRK to restore normal transmission.

5STKP

Stick Parity. When parity is enabled (PEN is 1), this bit and EPS (bit 4) control the parity

bit (see Table 5-59). This bit has no effect when parity is not enabled.

EPS

Even Parity Select. When parity is enabled (PEN is 1), this bit and STKP (bit 5) control the

parity bit (see Table 5-59). This bit has no effect when parity is not enabled.

PEN

Parity Enable. This bit enables the parity bit. The parity enable bit is used to produce an

even or odd number of 1s when the data bits and parity bit are summed, as an error detec-

tion device.

0: No parity bit is used (Default).

1: A parity bit is generated by the transmitter and checked by the receiver.

CS5535 数据表(PDF) 373 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 373 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载