CS5535 datasheet(377/555 Pages) NSC

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UART/IR Controller Register Descriptions (Continued)

MCR, Non-Extended Mode (EXCR1.EXT_SL = 0)

5.12.3.6

Link Status Register (LSR)

LSR provides status information concerning data transfer. Upon reset, this register assumes the value of 60h. The bit defi-

nitions change depending upon the operation mode of the functional block.

Bits 1 to 4 of the LSR indicate link status events. These bits are sticky (accumulate any conditions occurred since the last

time the register was read). They are cleared when one of the following events occur:

• Hardware reset

• Receiver soft reset (via the FIFO Control register)

• LSR register read

The LSR is intended for read operations only. Writing to the LSR is not permitted.

MCR Non-Extended Mode Register Map

RSVD

LOOP

ISEN or DCDLP

RILP

RTS

DTR

MCR Non-Extended Mode Bit Descriptions

Bit

Name

Description

7:5

RSVD

Reserved. Must written as 0.

4LOOP

Loopback Enable. This bit accesses the same internal register as LOOP (bit 4) of the

EXCR1 register. (See Section 5.12.5.2 on page 383 for more information on Loopback

mode).

0: Loopback disabled. (Default.)

1: Loopback enabled.

ISEN or

DCDLP

Interrupt Signal Enable or DCD Loopback. In normal operation (standard 16450 or 16550)

mode, this bit controls the interrupt signal and must be set to 1 in order to enable the inter-

rupt request signal. In loopback mode, this bit internally drives DCD, and the interrupt signal

is always enabled.

2RILP

Ring Indicator in Loopback. When loopback is enabled, this bit internally drives RI. Other-

wise, it is unused.

1RTS

Request To Send. When loopback is enabled, this bit drives CTS internally. Otherwise, it is

unused.

0DTR

Data Terminal Ready.When loopback is enabled, this bit internally drives DSR. Otherwise, it

is unused.

I/O Offset

05h

Type

Reset Value

60h

LSR Register Map

ER_INF

TXEMP

TXRDY

BRK

RXDA

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