 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS5535 数据表(PDF) 381 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
CS5535 数据表(HTML) 381 Page - National Semiconductor (TI) |
|
|
381 / 555 page  Revision 0.8 381 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.4 Bank 1 Register Descriptions The bit formats of the registers in Bank 1 are summarized in Table 5-36. Detailed descriptions of each register follow. 5.12.4.1 Legacy Baud Generator Divisor Port Legacy Baud Generator Divisor Low Byte (LBGD_L) Legacy Baud Generator Divisor High Byte (LBGD_H) The Legacy Baud Generator Divisor (LBGD) port provides an alternate data path to the Baud Divisor Generator register. LBGD is a 16-bit wide port split into two bytes, LBGD_L an LBGD_H, occupying consecutive address locations. This port is implemented to maintain compatibility with 16550 standard and to support existing legacy software packages. New soft- ware should use the BGD port in Bank 2 to access the baud generator divisor register. The programmable baud rates in the non-extended mode are achieved by dividing a 24 MHz clock by a prescale value of 13, 1.625 or 1. This prescale value is selected by the PRESL field of EXCR2 (Section 5.12.5.4 on page 385). Divisor values between 1 and 216-1 can be used (0 cannot be used, see Table 5-38 "Baud Generator Divisor Settings" on page 382). The baud generator divisor must be loaded during initialization to ensure proper operation of the baud genera- tor. Upon loading either part of it, the baud generator counter is immediately loaded. Table 5-38 shows typical baud divi- sors. After reset, the divisor register contents are indeterminate. If the UART is in extended mode, any access to the LBGD_L or LBGD_H causes a reset to the default non-extended mode (i.e., 16550 mode). To access a baud generator divisor when in extended mode, use the port pair in Bank 2 (see Section 5.12.5.1 "Baud Generator Divisor Port" on page 383). Table 5-37 shows the bits that are cleared when fallback occurs during extended or non-extended modes. If the UART is in non-extended mode and the LOCK bit is 1, the content of the divisor (BGD) port is not be effected and no other action is taken. Table 5-36. Bank 1 Bit Map Register Bits I/O Offset Name 765 4321 0 00h LBGD_L LBGD[7:0] 01h LBGD_H LBGD[15:8] 02h RSVD RSVD 03h LCR BKSE SBRK STKP EPS PEN STB WLS1 WLS0 BSR BKSE BSR[6:0] 04-07h RSVD RSVD I/O Offset 00h Type R/W Reset Value xxh I/O Offset 01h Type R/W Reset Value xxh Table 5-37. Bits Cleared on Fallback Register Name UART Mode and LOCK Bit before Fallback Extended Mode LOCK = x Non-Extended Mode LOCK = 0 Non-Extended Mode LOCK = 1 MCR 2 to 7 None None EXCR1 0, 5 and 7 5 and 7 None EXCR2 0 to 5 0 to 5 None IRCR1 2 and 3 None None |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
