CS5535 datasheet(385/555 Pages) NSC

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UART/IR Controller Register Descriptions (Continued)

Figure 5-2. DMA Control Signals Routing

5.12.5.3

Bank Select Register (BSR)

BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 5.12.3.4 "Link Control/Bank Select Regis-

ters" on page 373 for bit descriptions.

5.12.5.4

Extended Control Register 2 (EXCR2)

EXCR2 configures the RX_FIFO and TX_FIFO sizes and the value of the prescaler, and controls the baud divisor register

lock. Upon reset, all bits are set to 0.

Table 5-40. DMA Threshold Levels

Bit Value

DMA Threshold for FIFO Type

RX_FIFO

TX_FIFO

16 Levels

32 Levels

110

I/O Offset

03h

Type

R/W

Reset Value

00h

I/O Offset

04h

Type

R/W

Reset Value

00h

EXCR2 Register Map

LOCK

RSVD

PRESL[1:0]

RF_SIZ[1:0]

TF_SIZ[1:0]

EXCR2 Bit Descriptions

Bit

Name

Description

LOCK

Baud Divisor Register Lock. When set to 1, any access to the baud generator divisor

extended mode. In this case, two scratchpad registers overlaid with LBGD_L and

LBGD_H are enabled, and any attempted CPU access of the baud generator divisor reg-

ister through LBGD_L and LBGD_H access the scratchpad registers instead. This bit

must be set to 0 when extended mode is selected.

RSVD

Reserved. Write as 0.

Routing Logic

RX_DMA

RX-Channel

TX_DMA

DMA Handshake

Signals

DMASWP

DMA Swap Logic

Configuration Module

DMA Logic

TX-Channel

DMA Logic

Routing Logic

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