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数据搜索系统，热门电子元器件搜索 |
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CS5535 数据表(PDF) 389 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 389 Page - National Semiconductor (TI) |
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389 / 555 page  Revision 0.8 389 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.7 Bank 4 Register Descriptions The bit formats for the registers in Bank 4 are summarized in Table 5-42. Detailed descriptions of each register follow. 5.12.7.1 IR Control Register 1 (IRCR1) IRCR1 enables the Sharp-IR or SIR IR mode in non-extended mode of operation. Upon reset, all bits are set to 0. 5.12.7.2 Bank Select Register (BSR) BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 5.12.3.4 "Link Control/Bank Select Regis- ters" on page 373 for bit descriptions. Table 5-42. Bank 4 Bit Map Register Bits I/O Offset Name 76543210 00h-01h RSVD RSVD 02h IRCR1 RSVD IR_SL[1:0] RSVD 03h BSR BKSE BSR[6:0] 04h-07h RSVD RSVD I/O Offset 02h Type R/W Reset Value 00h IRCR1 Register Map 76 54 32 10 RSVD IR_SL[1:0] RSVD IRCR1 Bit Descriptions Bit Name Description 7:4 RSVD Reserved. Write as 0. 3:2 IR_SL[1:0] Sharp-IR or SIR Mode Select. These bits enable Sharp-IR and SIR modes in non- extended mode. They allow selection of the appropriate IR interface when extended mode is not selected. These bits are ignored when extended mode is selected. 00: UART (Default). 01: Reserved. 10: Sharp-IR. 11: SIR. 1:0 RSVD Reserved. Write as 0. I/O Offset 03h Type R/W Reset Value 00h |
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