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CS5535 数据表(PDF) 390 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 390 Page - National Semiconductor (TI) |
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390 / 555 page  www.national.com 390 Revision 0.8 UART/IR Controller Register Descriptions (Continued) 5.12.8 Bank 5 Register Descriptions The bit formats for the registers in Bank 5 are summarized in Table 5-43. Detailed descriptions of each register follow. 5.12.8.1 Bank Select Register (BSR) BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 5.12.3.4 "Link Control/Bank Select Regis- ters" on page 373 for bit descriptions. 5.12.8.2 IR Control Register 2 (IRCR2) IRCR2 controls the basic settings of the IR modes. Upon reset, the content of this register is 02h. Table 5-43. Bank 5 Bit Map Register Bits I/O Offset Name 76543210 00h-02h RSVD RSVD 03h BSR BKSE BSR[6:0] 04h IRCR2 RSVD RSVD RSVD AUX_IRRX RSVD RSVD IRMSSL IR_FDPLX 05h-07h RSVD RSVD I/O Offset 03h Type R/W Reset Value 00h I/O Offset 04h Type R/W Reset Value 02h IRCR2 Register Map 76 54 32 10 RSVD RSVD RSVD AUX_IRRX RSVD RSVD IRMSSL IR_FDPLX IRCR2 Bit Descriptions Bit Name Description 7:5 RSVD Reserved. Write to 0. 4 AUX_IRRX Auxiliary IR Input Select. When set to 1, the IR signal is received from the auxiliary input. See Table 5-51 "IR Receive Input Selection" on page 399. 3:2 RSVD Reserved. Write to 0. 1 IRMSSL MSR Register Function Select in IR Mode. This bit selects the behavior of the MSR and Modem Status Interrupt (MS_EV) when an IR mode is selected. When a UART mode is selected, the MSR and the MS_EV function normally and this bit is ignored. 0: MSR and MS_EV work in the IR modes as in the UART mode. 1: MSR returns 30h, and MS_EV is disabled (Default). 0IR_FDPLX Enable IR Full Duplex Mode. When set to 1, the IR receiver is not masked during trans- mission. |
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