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数据搜索系统，热门电子元器件搜索 |
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CS5535 数据表(PDF) 388 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 388 Page - National Semiconductor (TI) |
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388 / 555 page  www.national.com 388 Revision 0.8 UART/IR Controller Register Descriptions (Continued) 5.12.6.2 Shadow of Link Control Register (SH_LCR) SH_LCR returns the value of the LCR. The LCR is written into when a byte value, with bit 7 set to 0, is written to the LCR/BSR registers location (at I/O Offset 03h) from any bank. 5.12.6.3 Shadow of FIFO Control Register (SH_FCR) This register returns the contents of the FCR in Bank 0. 5.12.6.4 Bank Select Register (BSR) BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 5.12.3.4 "Link Control/Bank Select Regis- ters" on page 373 for bit descriptions. MRID Bit Descriptions Bit Name Description 7:4 MID[3:0] Module ID. Identifies the module type. 3:0 RID[3:0] Revision ID. Identifies the module revision level. For example, 0h = revision 0, 1h = revi- sion 1, etc. I/O Offset 01h Type RO Reset Value 00h SH_LCR Register Map 76 54 32 10 RSVD SBRK STKP EPS PEN STB WLS1 WLS0 I/O Offset 02h Type RO Reset Value 00h FCR Register Map 76 54 32 10 RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN I/O Offset 03h Type R/W Reset Value 00h |
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