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CS5535 数据表(PDF) 379 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 379 Page - National Semiconductor (TI) |
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379 / 555 page  Revision 0.8 379 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.3.7 Modem Status Register (MSR) The function of this register depends on the selected operational mode. When a UART mode is selected, this register pro- vides the current state as well as state-change information of the status lines from the modem or data transmission module. When any of the IR modes is selected, the register function is controlled by the setting of the IRMSSL bit of the IRCR2 (see Section 5.12.8.2 on page 390). If IRMSSL is 0, the MSR register works as in UART mode. If IRMSSL is 1, the MSR returns the value 30h, regardless of the state of the modem input lines. When loopback is enabled, the MSR works similarly except that its status input signals are internally driven by appropriate bits in the MCR since the modem input lines are internally disconnected. Refer to bits 1 to 0 in MCR extended mode or bits 3 to 0 in MCR non-extended mode (see Section 5.12.3.5 on page 376) and to the LOOP and ETDLBK bits at the EXCR1 (see Section 5.12.5.2 on page 383). A Modem Status Event (MS_EV) is generated if the MS_IE bit in IER is enabled and any of bits 0, 1, 2, or 3 in this register are set to 1. Bits 0 to 3 are cleared to 0 as a result of any of the following events: • A hardware reset occurs. • The operational mode is changed and the IRMSSL bit is 0. • The MSR register is read. In the reset state, bits 4 to 7 are indeterminate as they reflect their corresponding signal levels at MSR_UART[x]_MOD. I/O Offset 06h Type RO Reset Value x0h MSR (Modem Status Register) Register Map 76 54 32 10 DCD RI DSR CTS DDCD TERI DDSR DCTS MSR (Modem Status Register) Bit Descriptions Bit Name Description 7 DCD Data Carrier Detect. This is the status of the MOD5 bit in MSR_UART[x]_MOD (see Sec- tion 5.12.1.1 on page 363). 6RI Ring Indicator. This is the status of the MOD7 bit in MSR_UART[x]_MOD (see Section 5.12.1.1 on page 363). 5DSR Data Set Ready. This is the status of the MOD6 bit in MSR_UART[x]_MOD (see Section 5.12.1.1 on page 363). 4CTS Clear To Send. This is the status of the MOD4 bit in MSR_UART[x]_MOD (see Section 5.12.1.1 on page 363). 3 DDCD Delta Data Carrier Detect. This bit is the Delta Data Carrier Detect (DDCD) indicator. When high, this bit indicates that the DCD input has changed state. Reading this register causes this bit to be cleared. 2TERI Trailing Edge Ring Indicator. This bit is the Trailing Edge Ring Indicator (TERI) detector. When high, this bit indicates that the RI input has changed from a high to low state. Read- ing this register causes this bit to be cleared. 1 DDSR Delta Data Set Ready. This bit is the Delta Data Set Ready (DDSR) indicator. When high, this bit indicates that the DSR input has changed state since the last time it was read by the CPU. Reading this register causes this bit to be cleared. 0 DCTS Delta Clear To Send. This bit is the Delta Clear To Send (DCTS) indicator. When high, this bit indicates that the CTS input has changed state since the last time it was read by the CPU. Reading this register causes this bit to be cleared. |
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