CS5535 datasheet(365/555 Pages) NSC

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UART/IR Controller Register Descriptions (Continued)

5.12.1.3

UART[x] Interface Configuration (UART[x]_CONF)

UART1 Interface Configuration (UART[1]_CONF)

UART2 Interface Configuration (UART[2]_CONF)

UART[x]_CONF derives the control signals for mode and reset control.

MSR Address

5140003Ah

Type

R/W

Reset Value

42h

MSR Address

5140003Eh

Type

R/W

Reset Value

42h

UART[x]_CONF Register Map

RSVD

BUSY

RESET2SIR

EN_ BANKS

TEST

PWDN

DEVEN

MSR_SOFT_

RESET

UART[x]_CONF Bit Descriptions

Bit

Name

Description

RSVD

Reserved. Write as 0.

BUSY (RO)

Busy (Read Only). When high, this bit indicates that the UART busy signal is active.

RESET2SIR

IR Transmitter and Receiver Reset. Set to 1 to enable reset to the IR transmitter and

receiver. (Default = 0.) Write 0 to bring it out of reset.

EN_BANKS

Banks Enable. When set to 1, enables access to upper banks (i.e., Banks 2 through 7).

(Default = 0; that is, the UART boots in basic mode [16550 mode where access to upper

banks is not needed]).

TEST

Test. When set to 1, the UART goes into test mode and generates a baud clock on the

serial output pin UART[x]_TX (Default = 0.)

2PWDN

Power-down. When set to 1, the UART clocks (24 MHz clock) are frozen, but interrupt

remains enabled. (Default = 0.)

DEVEN

Device Enable. Set to 1 to enable the UART. Resetting this bit disables UART functional-

ity and masks the interrupt. (Default = 1.)

0MSR_SOFT_

RESET

MSR Software Reset. Writing a 1 resets the UART. (Default = 0.)

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