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CS5535 数据表(PDF) 367 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 367 Page - National Semiconductor (TI) |
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367 / 555 page  Revision 0.8 367 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.3 Bank 0 Register Descriptions In non-extended modes of operation, Bank 0 is compatible with both the 16450 and 16550. Upon reset, this functional block defaults to the 16450 mode. In extended mode, all the registers (except RXD and TXD) offer additional features. The bit for- mats for the registers in Bank 0 are summarized in Table 5-32. Detailed descriptions of each register follow. 5.12.3.1 Receive/Transmit Data Ports Receive Data Port (RXD) Transmit Data Port (TXD) The RXD (RO) and TXD (WO) ports share the same address. RXD is accessed during CPU read cycles. It is used to receive incoming data when the FIFOs are disabled, or from the bot- tom of the RX_FIFO when the FIFOs are enabled. TXD is accessed during CPU write cycles. It is used to write data directly to the transmitter when the FIFOs are disabled, or to the TX_FIFO when the FIFOs are enabled. DMA cycles always access the TXD and RXD ports, regardless of the selected bank. Table 5-32. Bank 0 Register Bit Map I/O Offset Name 7 654 3210 00h RXD RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 00h TXD TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 01h IER (Note 1) Note 1. Non-Extended Mode. RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER (Note 2) Note 2. Extended Mode. RSVD TXEMP_IE DMA_IE MS_IE LS_IE TXLDL_IE RXHDL_IE 02h EIR (Note 1) FEN[1:0] RSVD RXFT IPR[1:0] IPF EIR (Note 2) RSVD TXEMP_EV DMA_EV MS_EV LS_EV/ TXHLT_EV TXLDL_EV RXHDL_IE FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN 03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR BKSE BSR[6:0] 04h MCR (Note 1) RSVD LOOP ISEN or DCDLP RILP RTS DTR MCR (Note 2) MDSL[2:0] IR_PLS TX_DFR DMA_EN RTS DTR 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS 07h SPR (Note 1) Scratch Data ASCR (Note 2) CTE TXUR RXACT RXWDG RSVD S_OET RSVD RXF_TOUT I/O Offset 00h Type RO Reset Value xxh I/O Offset 00h Type WO Reset Value xxh |
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