M58PR256LE datasheet(53/119 Pages) STMICROELECTRONICS

部件名	M58PR256LE

功能描述	256-Mbit, 512-Mbit or 1-Gbit (횞 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories

PDF	119 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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53 / 119 page

M58PR256LE, M58PR512LE, M58PR001LE

Configuration Register

53/119

In the worst case scenario, the number of wait states is one clock cycle less than the latency

setting. Wait is asserted only once during a continuous burst access. See also Table 17:

Burst type definition.

CR9, CR7, CR6, CR5, CR4 and CR3 are reserved for future use.

Table 16.

Configuration Register

Bit

Description

Value

Description

CR15

Read Select

Synchronous read

Asynchronous read (default at power-on)

CR14-CR11

X latency

0011

3 Clock latency

0100

4 Clock latency

0101

5 Clock latency

0110

6 Clock latency

0111

7 Clock latency

1000

8 Clock latency

1001

9 Clock latency

1010

10 Clock latency

1011

11 Clock latency

1100

12 Clock latency

1101

13 Clock latency

1110

14 Clock latency

1111

15 Clock latency (default)

Other configurations reserved

CR10

Wait polarity

WAIT is active Low (default)

WAIT is active High

CR9

Reserved(1)

Reserved bits should be cleared to ‘0’.

CR8

Wait

configuration

WAIT is active during wait state

WAIT is active one data cycle before wait state (default)1

CR7-CR3

Reserved(1)

CR2-CR0

Burst length

010

8 words (wrap only)

011

16 words (wrap only)

111

Continuous (default, no wrap only)

M58PR256LE 数据表(PDF) 53 Page - STMicroelectronics

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