M58PR256LE datasheet(24/119 Pages) STMICROELECTRONICS

24 / 119 page

Command interface

M58PR256LE, M58PR512LE, M58PR001LE

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4.5

Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1,

SR3, SR4, SR5, SR8 and SR9) in the Status Register.

One bus write cycle is required to issue the Clear Status Register command. The Clear

Status Register command does not affect the read mode of the bank.

The error bits in the Status Register do not automatically return to ‘0’ when a new command

is issued. The error bits in the Status Register should be cleared before attempting a new

program or erase command.

4.6

Block Erase command

The Block Erase command erases a block. It sets all the bits within the selected block to ’1’,

and all previous data in the block is lost.

If the block is protected then the erase operation aborts, the data in the block is not

changed, and the Status Register outputs the error.

Two bus write cycles are required to issue the command.

●

The first bus cycle sets up the Block Erase command.

●

The second latches the block address and starts the Program/Erase Controller.

If the second bus cycle is not the block erase confirm code, Status Register bits SR4 and

SR5 are set and the command is aborted.

Once the command is issued, the bank enters Read Status Register mode and any read

operation within the addressed bank outputs the contents of the Status Register. A Read

Array command is required to return the bank to read array mode.

During block erase operations the bank containing the block being erased only accepts the

Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the

Program/Erase Suspend command; all other commands are ignored.

The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be

guaranteed when the block erase operation is aborted, the block must be erased again.

Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks

not being erased.

Typical erase times are provided in Table 23: Program/erase times and endurance cycles.

See Appendix C, Figure 23: Block erase and EFA block erase flowchart and pseudocode for

a suggested flowchart for using the Block Erase command.

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