M58PR256LE datasheet(51/119 Pages) STMICROELECTRONICS

51 / 119 page

M58PR256LE, M58PR512LE, M58PR001LE

Configuration Register

51/119

Configuration Register

The Configuration Register configures the type of bus access that the memory performs.

Refer to Section 10: Read modes for details on read operations.

The Configuration Register is set through the command interface using the Set

Configuration Register command. The Configuration Register is volatile: after a reset or a

power-down/power-up sequence, the register is set for asynchronous read (CR15=1) and all

bits return to their default value. The Configuration Register bits are described in Table 16.

They specify the selection of the burst length, burst X latency and the read operation. Refer

to Figure 6 and Figure 7 for examples of synchronous burst configurations.

7.1

Read select bit (CR15)

The read select bit, CR15, switches between asynchronous and synchronous read

operations.

When:

●

CR15 = 0:

–

Read operations in the main array are performed in synchronous burst mode,

–

Operations to read the Status Register, electronic signature, CFI and EFA are

performed in single synchronous mode (See Section 10.3: Single synchronous

read mode for details).

●

CR15 = 1:

–

Read operations in the main array are performed in Asynchronous page mode,

–

Operations to read the Status Register, electronic signature, CFI and EFA are

performed in asynchronous random access mode.

Synchronous burst read can be performed across banks.

On reset or power-up the read select bit is set to ’1’ for asynchronous access.

7.2

X latency bits (CR14-CR11)

The X latency bits are used during synchronous read operations to set the number of clock

cycles between the address being latched and the first data becoming available.

For correct operation the X latency bits can only assume the values in Table 16:

Configuration Register.

Table 15 shows how to set the X latency parameter, taking into account the frequency used

to read the Flash memory in synchronous mode.

Refer to Figure 6: X latency and data output configuration example for an example

waveform.

M58PR256LE 数据表(PDF) 51 Page - STMicroelectronics

M58PR256LE 数据表(HTML) 51 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载