M58PR256LE datasheet(18/119 Pages) STMICROELECTRONICS

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Bus operations

M58PR256LE, M58PR512LE, M58PR001LE

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Bus operations

There are seven standard bus operations that control the device. These are Bus Read, Bus

Write, Address Latch, Output Disable, Standby, Reset and deep power-down. See Table 6:

Bus operations, for a summary.

Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus write operations.

3.1

Bus Read

Bus Read operations are used to output the contents of the memory array, the Electronic

signature, the Status Register and the common Flash interface. Both Chip Enable and

Output Enable must be at VIL in order to perform a read operation. The Chip Enable input

should be used to enable the device. Output Enable should be used to gate data onto the

output. The data read depends on the previous command written to the memory (see

Section 4: Command interface). See figures 10, 11, 12 and 13, Read AC waveforms, and

tables 29 and 30, Read AC characteristics, for details of when the output becomes valid.

3.2

Bus Write

Bus Write operations write commands to the memory or latch input data to be programmed.

A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output

Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to

the Write operation by toggling Latch Enable. In this case the Latch Enable should be tied to

VIH during the Bus Write operation.

See figures 15 and 16, Write AC waveforms, and tables 31 and 32, Write AC characteristics,

for details of the timing requirements.

3.3

Address Latch

Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must

be at VIL during Address Latch operations. The addresses are latched on the rising edge of

Latch Enable.

3.4

Output Disable

The outputs are high impedance when the Output Enable is at VIH.

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