M58PR256LE datasheet(100/119 Pages) STMICROELECTRONICS

100 / 119 page

Common Flash interface

M58PR256LE, M58PR512LE, M58PR001LE

100/119

Table 52.

Extended Flash array bank and erase block region 1 information

Offset(1)

Data

Description

(P+3A)h = 144h

16h

Data size of this bank region information section (addressable locations

including this one)

(P+3B)h = 145h

00h

(P+3C)h = 146h

01h

Number of identical banks within bank region 1

(P+3D)h = 147h

00h

(P+3E)h = 148h

11h

Number of program or erase operations allowed in bank region 1:

Bits 0-3: number of simultaneous program operations

Bits 4-7: number of simultaneous erase operations

(P+3F)h = 149h

00h

Number of program or erase operations allowed in other banks while a

bank in this region is being erased

Bits 0-3: number of simultaneous program operations

Bits 4-7: number of simultaneous erase operations

(P+40)h = 14Ah

00h

Number of program or erase operations allowed in other banks while a

bank in this region is being erased

Bits 0-3: number of simultaneous program operations

Bits 4-7: number of simultaneous erase operations

(P+41)h = 14Bh

01h

Types of erase block regions in bank region 1

n = number of erase block regions with contiguous same-size erase

blocks.

Symmetrically blocked banks have one blocking region(2).

(P+42)h = 14Ch

03h

Bank region 1 Erase block type 1 information

Bits 0-15: n+1 = number of identical-sized erase blocks in each bank

Bits 16-31: n×256 = number of bytes in erase block region

(P+43)h = 14Dh

00h

(P+44)h = 14Eh

20h

(P+45)h = 14Fh

00h

(P+46)h = 150h

64h

Bank region 1 (Erase block type 1)

Minimum block erase cycles × 1000

(P+47)h = 151h

00h

(P+48)h = 152h

01h

Bank region 1 (Erase block type 1): bits per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for internal ECC used

BIts 5-7: reserved

(P+49)h = 153h

03h

Bank region 1 (Erase block type 1): page mode and synchronous mode

capabilities

Bit 0: page-mode reads permitted

Bit 1: synchronous reads permitted

Bit 2: synchronous writes permitted

Bits 3-7: reserved

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