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M58PR256LE 数据表(PDF) 26 Page - STMicroelectronics

部件名 M58PR256LE
功能描述  256-Mbit, 512-Mbit or 1-Gbit (횞 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
PDF  119 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M58PR256LE 数据表(HTML) 26 Page - STMicroelectronics

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Command interface
M58PR256LE, M58PR512LE, M58PR001LE
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4.8
Buffer Program command
The Buffer Program command uses the device’s 1 Kbyte write buffer to speed up
programming. Up to 1 Kbyte can be loaded into the write buffer and programmed into the
specified 1 Kb aligned location in the main array. The Buffer Program command dramatically
reduces in-system programming time compared to the standard non-buffered program
command.
The Buffer Program command is supported in both object program mode and control
program mode.
When using the Buffer Program command in a region configured in object mode, the start
programming address must be aligned to the 1 Kb buffer.
When using the Buffer Program command in a region configured in control program mode,
the programmed address must be within the ’A’ segment halves of the program region
(addresses with A3 = 0) and the ’B’ segment halves of the program region (addresses with
A3 = 1) must be filled only with FFFFh data.
Before issuing the Buffer Program Setup command, the Status Register bit SR7 at the bank
address should be read to ensure that the buffer is available (SR7=1).
Four successive steps are required to issue the Buffer Program command:
1.
The first bus write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
2.
The second bus write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed. The maximum buffer count is 1FF (512 words).
3.
Use n+1 bus write cycles to load the address and data for each word into the write
buffer. Addresses must lie within the range from the start address to the start address +
n, where the start address is the location of the first data to be programmed. The start
address must be aligned to a 1 Kb boundary.
4.
The final bus write cycle confirms the Buffer Program command and starts the program
operation.
All the addresses used in the buffer program operation must lie within the same block.
The buffer program operation does not change the read status of the banks until the Buffer
Program Confirm command is issued. The Buffer Program Confirm command changes the
read status of the bank to read Status Register, therefore, after the Buffer Program Confirm
command, read operations in the bank output the contents of the Status Register.
Invalid address combinations or failure to follow the correct sequence of bus write cycles
sets an error in the Status Register and aborts the operation without affecting the data in the
memory array.
If the block being programmed is protected, an error is set in the Status Register and the
operation aborts without affecting the data in the memory array.
During buffer program operations the bank being programmed only accepts the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend commands; all other commands are ignored.
Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks
not being programmed.
See Appendix C, Figure 21: Buffer program flowchart and pseudocode for a suggested
flowchart on using the Buffer Program command.



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