M58PR256LE datasheet(32/119 Pages) STMICROELECTRONICS

32 / 119 page

Command interface

M58PR256LE, M58PR512LE, M58PR001LE

32/119

4.16

Block Lock-down command

The Block Lock-down command locks down a locked or unlocked block.

A locked-down block cannot be programmed or erased. The lock status of a locked-down

block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function

is disabled and the locked blocks can be individually unlocked by the Block Unlock

command.

Two bus write cycles are required to issue the Block Lock-down command.

●

The first bus cycle sets up the Block Lock-down command.

●

The second bus write cycle latches the block address and locks-down the block.

The lock status can be monitored for each block using the Read Electronic Signature

command.

Locked-down blocks revert to the locked (and not locked-down) state when the device is

reset on power-down. Table 22 shows the Lock Status after issuing a Block Lock-down

command.

Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 25:

Main array and EFA locking operations flowchart and pseudocode for a flowchart for using

the Lock-down command.

4.17

Blank Check command

The Blank Check command checks whether a main array block has been completely

erased. Only one block at a time can be checked. Two bus cycles are required to issue the

Blank Check command:

●

The first bus cycle writes the Blank Check command to any address in the block to be

checked.

●

The second bus cycle writes the Blank Check Confirm command (D0h) to any address

in the block to be checked and starts the blank check operation.

If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are

set to ‘1’ and the command aborts.

Once the command is issued the addressed bank automatically enters the Status Register

mode and further reads within the bank output the Status Register contents.

The only operation permitted during blank check is Read Status Register. Dual operations

are not supported while a blank check operation is in progress. Blank check operations

cannot be suspended and are not allowed while the device is in program/erase suspend.

The SR7 Status Register bit indicates the status of the blank check operation in progress:

SR7 = ‘0’ means that the blank check operation is still ongoing. SR7 = ‘1’ means that the

operation is complete.

The SR5 Status Register bit goes High (SR5 = ‘1’) to indicate that a blank check operation

has failed.

At the end of the operation the bank remains in the Read Status Register mode until another

command is written to the command interface.

See Appendix C, Figure 26: Blank check flowchart and pseudocode for a suggested

flowchart for using the Blank Check command.

Typical Blank Check times are provided in Figure 23: Program/erase times and endurance

cycles.

M58PR256LE 数据表(PDF) 32 Page - STMicroelectronics

M58PR256LE 数据表(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

M58PR256LE 数据表(PDF) 32 Page - STMicroelectronics

M58PR256LE 数据表(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载