M58PR256LE datasheet(28/119 Pages) STMICROELECTRONICS

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Command interface

M58PR256LE, M58PR512LE, M58PR001LE

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4.9.2

Program and verify phase

The program and verify phase requires 512 cycles to program the 512 words to the write

buffer. The data is stored sequentially, starting at the first address of the write buffer, until the

write buffer is full (512 words). To program less than 512 words, the remaining words should

be programmed with FFFFh.

Three successive steps are required to issue and execute the program and verify phase of

the command.

Use one bus write operation to latch the start address and the first word to be

programmed. The Status Register Bank write status bit SR0 should be read to check

that the P/EC is ready for the next word.

Each subsequent word to be programmed is latched with a new bus write operation.

The address must remain the start address as the P/EC increments the address

location. If any address is given that is not in the same block as the start address, the

program and verify phase terminates. Status Register bit SR0 should be read between

each bus write cycle to check the P/EC is ready for the next word.

Once the write buffer is full, the data is programmed sequentially to the memory array.

After the program operation the device automatically verifies the data and reprograms if

necessary.

The program and verify phase can be repeated, without re-issuing the command, to

program additional 512 word locations as long as the address remains in the same block.

Finally, after all words, or the entire block have been programmed, write FFFFh to any

address outside the block containing the start address to terminate the program and

verify phase.

Status Register bit SR0 must be checked to determine whether the program operation is

finished. The Status Register may be checked for errors at any time but it must be checked

after the entire block has been programmed.

4.9.3

Exit phase

When Status Register P/EC bit SR7 is set to ‘1’ this indicates that the device has exited the

buffer enhanced factory program operation.

Upon exiting the buffered enhanced factory program algorithm by writing FFFFh to an

address outside the block containing the start address, the Read mode of the programmed

and addressed banks remains unchanged.

A full Status Register check should be done to ensure that the block has been successfully

programmed. See Chapter 6: Status Register for more details.

For optimum performance the Buffer Enhanced Factory Program command should be

limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the

internal algorithm continues to work properly but some degradation in performance is

possible. Typical program times are provided in Table 23.

See Appendix C, Figure 28: Buffer enhanced factory program flowchart and pseudocode for

a suggested flowchart on using the Buffer Enhanced Factory Program command.

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