M58PR256LE datasheet(33/119 Pages) STMICROELECTRONICS

33 / 119 page

M58PR256LE, M58PR512LE, M58PR001LE

Command interface

33/119

4.18

Set Enhanced Configuration Register command

The Set Enhanced Configuration Register command is used to write a new value to the

Enhanced Configuration Register. Two bus write cycles are required to issue the Set

Enhanced Configuration Register command.

●

The first cycle sets up the Set Enhanced Configuration Register command and the

address corresponding to the Enhanced Configuration Register contents.

●

The second cycle writes the Enhanced Configuration Register data and the Confirm

command.

The Enhanced Configuration Register data must be written as an address during the bus

write cycle, such as A0 = ECR0, A1 = ECR1, …, A15 = ECR15.

If the Set Enhanced Configuration Register setup write cycle is not followed by the Set

Enhanced Configuration Register Confirm command (04h), Status Register bits SR4 and

SR5 are set.

After successfully executing this command, the bank addressed returns to read array state.

4.19

Read EFA Block command

The Read EFA Block command places the addressed bank in the read EFA mode, where all

addresses in the addressed bank are remapped to EFA block addresses.

When the device is in read EFA mode, the main array blocks in the addressed bank can no

longer be accessed until a Read Array command is issued to the bank.

One bus write cycle is required to issue the Read EFA Block command. Once a bank is in

read EFA mode, subsequent read operations from any address within the EFA block output

the EFA data from the EFA block. See Table 5: EFA memory map for details.

EFA blocks can be read through asynchronous or single synchronous read operations only.

The Asynchronous page read mode cannot be used to read the EFA blocks.

If a Read EFA command is issued in a bank that is programming or erasing, the read mode

of the bank changes to Read EFA mode.

M58PR256LE 数据表(PDF) 33 Page - STMicroelectronics