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M58PR256LE 数据表(PDF) 19 Page - STMicroelectronics |
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M58PR256LE 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 119 page ![]() M58PR256LE, M58PR512LE, M58PR001LE Bus operations 19/119 3.5 Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. 3.6 Reset During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. 3.7 Deep power-down (DPD) The memory enters the deep power-down mode from the Standby mode (RP and E are de- asserted, VIH) by setting ECR15 High (set to ‘1’) and asserting the DPD pin (these two events can be done in any order). The DPD pin polarity is determined by the value of ECR14 when: ● ECR14 is cleared (‘0’) the DPD pin is active Low. The DPD pin is active Low by default. ● ECR14 is set (‘1’), the DPD pin is active High. While in DPD mode, the: ● Values of the Configuration Register, Enhanced Configuration Register, block lock bits, and bank states are preserved. ● Status Register is reset to 80h. If the Status Register contains errors before entering the DPD mode, the error bits are lost after exiting DPD mode. The device should not be put in deep power-down mode while a program, erase or suspend operation is in progress, otherwise the operation aborts, and the memory contents are no longer valid. The deep power-down mode is exited tDPHEL after de-asserting the DPD pin. Upon exiting the deep power-down mode, the memory reverts to standby mode. If the RP pin is asserted while in DPD mode, the device exits DPD mode after tPHEL and ECR15 is reset to 0. |
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