M58PR256LE datasheet(46/119 Pages) STMICROELECTRONICS

46 / 119 page

Status Register

M58PR256LE, M58PR512LE, M58PR001LE

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Status Register

The Status Register provides information on the current or previous program or erase

operations. Issue a Read Status Register command to read the contents of the Status

To output the contents, the Status Register is latched and updated on the falling edge of the

Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable

returns to VIH.

The Status Register can only be read using single asynchronous or single synchronous

reads.

Bus read operations from any address within the bank always read the Status Register

during program and erase operations if no Read Array command has been issued.

The various bits convey information about the status and any errors of the operation. Bits

SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset

by the device. Bits SR9, SR8, SR5, SR4, SR3 and SR1 give information on errors. They are

set by the device but must be reset by issuing a Clear Status Register command or a

hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing

another command.

The bits in the Status Register are summarized in Table 14: Status Register bits. Refer to

Table 14 in conjunction with the following text descriptions.

6.1

Control program mode status bit (SR9)

The control program mode status bit, SR9, indicates whether an error occurred while writing

to a program region that is configured in control program mode.

The SR9 bit should be read once the Program/Erase Controller status bit SR7 is set to ‘1’

(Program/Erase Controller inactive).

SR9 is set to 1 when the user attempts to program object data in a control mode region.

When:

●

SR9 = 0, the program operation completed successfully.

●

SR9 = 1, the program operation failed.

Once set to ‘1’, SR9 can only be cleared by issuing a Clear Status Register command or

through a hardware reset.

SR9 should be cleared before a new program command is issued, otherwise the new

command appears to fail.

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