MPC8360 datasheet(22/112 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

DDR and DDR2 SDRAM

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20 and Table 21 provide the output AC timing specifications and measurement conditions for the

DDR and DDR2 SDRAM interface.

AC input high voltage

VIH

MVREF + 0.31

—

Notes:

1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if

≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).

Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V

At recommended operating conditions with GVDD of 2.5 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

MDQS—MDQ/MECC input skew per byte

333 MHz

266 MHz

200 MHz

tDISKEW

-750

-1125

-1250

750

1125

1250

1, 2

Notes:

1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if

≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode

At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.

Parameter 8

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)

tMCK

610

Skew between any MCK to ADDR/CMD

333 MHz

266 MHz

200 MHz

tAOSKEW

-1.0

-1.1

-1.2

0.2

0.3

0.4

ADDR/CMD output setup with respect to MCK

333 MHz

266 MHz

200 MHz

tDDKHAS

2.1

2.8

3.5

—ns

ADDR/CMD output hold with respect to MCK

333 MHz

266 MHz - DDR1

266 MHz - DDR2

200 MHz

tDDKHAX

2.0

2.72.8

3.5

—ns

MCS(n) output setup with respect to MCK

333 MHz

266 MHz

200 MHz

tDDKHCS

2.1

2.8

3.5

—ns

Table 18. DDR SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V (continued)

At recommended operating conditions with GVDD of 2.5 V ± 5%.

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