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MPC8360 数据表(PDF) 24 Page - Freescale Semiconductor, Inc |
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MPC8360 数据表(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 112 page  MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 24 Freescale Semiconductor DDR and DDR2 SDRAM Figure 6 shows the DDR SDRAM output timing for address skew with respect to any MCK. Figure 6. Timing Diagram for tAOSKEW Measurement Figure 7 provides the AC test load for the DDR bus. Figure 7. DDR AC Test Load Table 21. DDR and DDR2 SDRAM Measurement Conditions Symbol DDR DDR2 Unit Notes VTH MVREF ± 0.31 V MVREF ± 0.25 V V 1 VOUT 0.5 × GVDD 0.5 × GVDD V2 Notes: 1. Data input threshold measurement point. 2. Data output measurement point. ADDR/CMD MCK[n] MCK[n] tMCK tAOSKEW(max) CMD NOOP tAOSKEW(min) ADDR/CMD CMD NOOP Output Z0 = 50 Ω GVDD/2 RL = 50 Ω |
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