MPC8360 datasheet(64/112 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

HDLC, BISYNC, Transparent, and Synchronous UART

19.1

HDLC, BISYNC, Transparent, and Synchronous UART DC

Electrical Characteristics

Table 61 provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and

synchronous UART protocols.

19.2

HDLC, BISYNC, Transparent, and Synchronous UART AC Timing

Specifications

Table 62 and Table 63 provide the input and output AC timing specifications for HDLC, BiSync,

transparent, and synchronous UART protocols.

Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH = –2.0 mA

2.4

—

Output low voltage

VOL

IOL = 3.2 mA

—

0.5

Input high voltage

VIH

—2.0

OVDD + 0.3

Input low voltage

VIL

—

–0.3

0.8

Input current

IIN

0 V

≤ VIN ≤ OVDD

—±10

μA

Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Outputs—Internal clock delay

tHIKHOV

11.2

Outputs—External clock delay

tHEKHOV

10.8

Outputs—Internal clock High Impedance

tHIKHOX

-0.5

5.5

Outputs—External clock High Impedance

tHEKHOX

Inputs—Internal clock input setup time

tHIIVKH

8.5

—

Inputs—External clock input setup time

tHEIVKH

4—

Inputs—Internal clock input Hold time

tHIIXKH

1.4

—

Inputs—External clock input hold time

tHEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high

state (H) until outputs (O) are invalid (X).

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