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MPC8360 数据表(PDF) 62 Page - Freescale Semiconductor, Inc |
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MPC8360 数据表(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 112 page ![]() MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 62 Freescale Semiconductor UTOPIA/POS 18 UTOPIA/POS This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8360E/58E. 18.1 UTOPIA/POS DC Electrical Characteristics Table 59 provides the DC electrical characteristics for the device UTOPIA. 18.2 Utopia/POS AC Timing Specifications Table 60 provides the UTOPIA input and output AC timing specifications. Table 59. UTOPIA DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Input high voltage VIH —2.0 OVDD + 0.3 V Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V ≤ VIN ≤ OVDD —±10 μA Table 60. UTOPIA AC Timing Specifications1 Characteristic Symbol 2 Min Max Unit Notes UTOPIA outputs—Internal clock delay tUIKHOV 011.5 ns UTOPIA outputs—External clock delay tUEKHOV 111.6 ns UTOPIA outputs—Internal clock High Impedance tUIKHOX 08.0 ns UTOPIA outputs—External clock High Impedance tUEKHOX 110.0 ns UTOPIA inputs—Internal clock input setup time tUIIVKH 6— ns UTOPIA inputs—External clock input setup time tUEIVKH 4— ns 3 UTOPIA inputs—Internal clock input Hold time tUIIXKH 2.4 — ns UTOPIA inputs—External clock input hold time tUEIXKH 1— ns 3 Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). 3. In rev 2.0 silicon, due to errata, tUEIVKH minimum is 4.3 ns and tUEIXKH minimum is 1.4 ns under specific conditions. Please refer to QE_UPC3 in the device errata document. |
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