MPC8360 datasheet(61/112 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

TDM/SI

Figure 43 provides the AC test load for the TDM/SI.

Figure 43. TDM/SI AC Test Load

Figure 44 represents the AC timing from Table 56. Note that although the specifications generally

reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the

active edge.

Figure 44 shows the TDM/SI timing with external clock.

Figure 44. TDM/SI AC Timing (External Clock) Diagram

TDM/SI inputs—External clock input hold time

tSEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes

from the high state (H) until outputs (O) are invalid (X).

3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and

SITXCEI[TXCEIx]. See the

MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more

details.

Table 58. TDM/SI AC Timing Specifications1 (continued)

Characteristic

Symbol2

Min

Max3

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

TDM/SICLK (input)

tSEIXKH

tSEIVKH

tSEKHOV

Input Signals:

TDM/SI

(See Note)

Output Signals:

TDM/SI

(See Note)

tSEKHOX

Note: The clock edge is selectable on TDM/SI

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