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MPC8360 数据表(PDF) 94 Page - Freescale Semiconductor, Inc |
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MPC8360 数据表(HTML) 94 Page - Freescale Semiconductor, Inc |
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94 / 112 page ![]() MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 94 Freescale Semiconductor Clocking NOTE Core VCO frequency = Core frequency × VCO divider. VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. Having a core frequency below the CSB frequency is not a possible option because the core frequency must be equal to or greater than the CSB frequency. 10 0001 01:1 ÷8 11 0001 01:1 ÷8 00 0001 1 1.5:1 ÷2 01 0001 1 1.5:1 ÷4 10 0001 1 1.5:1 ÷8 11 0001 1 1.5:1 ÷8 00 0010 02:1 ÷2 01 0010 02:1 ÷4 10 0010 02:1 ÷8 11 0010 02:1 ÷8 00 0010 1 2.5:1 ÷2 01 0010 1 2.5:1 ÷4 10 0010 1 2.5:1 ÷8 11 0010 1 2.5:1 ÷8 00 0011 03:1 ÷2 01 0011 03:1 ÷4 10 0011 03:1 ÷8 11 0011 03:1 ÷8 Table 73. e300 Core PLL Configuration (continued) RCWL[COREPLL] core_clk : csb_clk Ratio VCO divider 0-1 2-5 6 |
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