MPC8360 datasheet(25/112 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

DDR and DDR2 SDRAM

Figure 8 shows the DDR SDRAM output timing diagram for source synchronous mode.

Figure 8. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

Table 22 provides approximate delay information that can be expected for the address and command

signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.

These numbers are the result of simulations for one topology. The delay numbers will strongly depend on

the topology used. These delay numbers show the total delay for the address and command to arrive at the

DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the

system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup

requirements at the DRAM.

Table 22. Expected Delays for Address/Command

Load

Delay

Unit

4 devices (12 pF)

3.0

9 devices (27 pF)

3.6

36 devices (108 pF) + 40 pF compensation capacitor

5.0

36 devices (108 pF) + 80 pF compensation capacitor

5.2

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

tMCK

tDDKLDX

tDDKHDX

tDDKHAX ,tDDKHCX

Write A0

NOOP

tDDKHME

tDDKHMP

MPC8360 数据表(PDF) 25 Page - Freescale Semiconductor, Inc

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