MPC8360 datasheet(88/112 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

Clocking

Figure 54 shows the internal distribution of clocks within the MPC8358E.

Figure 54. MPC8358E Clock Subsystem

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on

whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary

clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKEN]. When the

device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected

(RCWH[PCICKEN] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (

÷2) and

the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input

selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn]

parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.The

OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn respectively.

Core PLL

System

LBIU

LSYNC_IN

LSYNC_OUT

LCLK[0:2]

core_clk

e300 core

csb_clk to rest

CLKIN

csb_clk

MPC8358E

Local Bus

PCI_CLK_OUT[0:2]

PCI_SYNC_OUT

PCI_CLK/

Clock

Unit

of the device

lb_clk

CFG_CLKIN_DIV

PCI Clock

PCI_SYNC_IN

Memory

Device

DLL

Divider

MEMC1_MCK[0:5]

DDRC

ddr1_clk

DDRC

Memory

Device

PLL

QUICC

PLL

ce_clk to QUICC Engine block

Engine

MPC8360 数据表(PDF) 88 Page - Freescale Semiconductor, Inc

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