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MPC8360 数据表(PDF) 36 Page - Freescale Semiconductor, Inc |
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MPC8360 数据表(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 112 page  MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 36 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 18 shows the TBI receive AC timing diagram. Figure 18. TBI Receive AC Timing Diagram 8.2.5 RGMII and RTBI AC Timing Specifications Table 35 presents the RGMII and RTBI AC timing specifications. Table 35. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LVDD of 2.5 V ± 5%. Parameter/Condition Symbol1 Min Typ Max Unit Notes Data to clock output skew (at transmitter) tSKRGTKHDX tSKRGTKHDV –0.5 — —— 0.5 ns 7 Data to clock input skew (at receiver) tSKRGDXKH tSKRGDVKH 1.0 — —— 2.6 ns 2 Clock cycle duration tRGT 7.2 8.0 8.8 ns 3 Duty cycle for 1000Base-T tRGTH/tRGT 45 50 55 % 4, 5 Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 5 Rise time (20%–80%) tRGTR — — 0.75 ns Fall time (20%–80%) tRGTF — — 0.75 ns GTX_CLK125 reference clock period tG125 —8.0 — ns 6 PMA_RX_CLK1 RCG[9:0] tTRX tTRXH tTRXR tTRXF tTRDVKH PMA_RX_CLK0 tTRDXKH tTRDVKH tTRDXKH tSKTRX tTRXH Even RCG Odd RCG |
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