MPC8360 datasheet(17/112 Pages) FREESCALE

17 / 112 page

MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

RESET Initialization

5.1

RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins of the device.

5.2

RESET AC Electrical Characteristics

This section describes the AC electrical specifications for the reset initialization timing requirements of

the device. Table 10 provides the reset initialization AC timing specifications for the DDR SDRAM

component(s).

Table 9. RESET Pins DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

2.0

OVDD + 0.3

Input low voltage

VIL

–0.3

0.8

Input current

IIN

±10

μA

Output high voltage

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Notes:

1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE.

2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET

(input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable

clock applied to CLKIN when the device is in PCI host

mode

—

tCLKIN

Required assertion time of PORESET with stable

clock applied to PCI_SYNC_IN when the device is in

PCI agent mode

—

tPCI_SYNC_IN

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR config signals

(CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of

PORESET when the device is in PCI host mode

4—

tCLKIN

Input setup time for POR config signals

(CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of

PORESET when the device is in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR config signals with respect to

negation of HRESET

0—

MPC8360 数据表(PDF) 17 Page - Freescale Semiconductor, Inc

MPC8360 数据表(HTML) 17 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

MPC8360 数据表(PDF) 17 Page - Freescale Semiconductor, Inc

MPC8360 数据表(HTML) 17 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载