MPC8360 datasheet(91/112 Pages) FREESCALE

部件名	MPC8360

功能描述	PowerQUICC??II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

Clocking

22.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. Table 70 shows the

multiplication factor encodings for the system PLL.

The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 71.

NOTE

The VCO divider must be set properly so that the system VCO frequency is

in the range of 600-1400 MHz.

The system VCO frequency is derived from the following equations:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

Table 70. System PLL Multiplication Factors

RCWL[SPMF]

System PLL Multiplication

Factor

0000

× 16

0001

Reserved

0010

× 2

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111

× 7

1000

× 8

1001

× 9

1010

× 10

1011

× 11

1100

× 12

1101

× 13

1110

× 14

1111

× 15

Table 71. System PLL VCO Divider

RCWL[SVCOD]

VCO Divider

Reserved

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