MPC8360 datasheet(18/112 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2

Freescale Semiconductor

RESET Initialization

Table 11 provides the PLL and DLL lock times.

5.3

QE Operating Frequency Limitations

This section specify the limits of the AC electrical characteristics for the operation of the QE’s

communication interfaces.

NOTE

The settings listed below are required for correct hardware interface

operation. Each protocol by itself requires a minimal QE operating

frequency setting for meeting the performance target. Because the

performance is a complex function of all the QE settings, the user should

make use of the QE performance utility tool provided by Freescale to

validate their system.

Table 12 lists the maximal QE I/O frequencies and the minimal QE core frequency for each interface.

Time for the device to turn off POR config signals with

respect to the assertion of HRESET

—4

Time for the device to turn on POR config signals with

respect to the negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode

the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of

CFG_CLKIN_DIV. See the

MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more

details.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode.

See the

MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 11. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs

DLL lock times

7680

122,880

csb_clk cycles

1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk).

A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.

Table 12. QE Operating Frequency Limitations

Interface

Interface Operating

Frequency (MHz)

Max interface

Bit Rate (Mbps)

Min QE Operating

Frequency1 (MHz)

Notes

Ethernet Management:

MDC/MDIO

10 (max)

MII

25 (typ)

100

Table 10. RESET Initialization Timing Specifications (continued)

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