ST92F120JR9T datasheet(238/320 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C INTERFACE (Cont’d)

INTERRUPT STATUS REGISTER (I2CISR)

R248 - Read / Write

Reset Value: 1xxx xxxx (xxh)

Bit 7 = DMASTOP

DMA suspended mode.

This bit selects between DMA suspended mode

and DMA not suspended mode.

In DMA Suspended mode, if the error interrupt

pending bit (I2CISR.IERRP) is set, no DMA re-

quest is performed. DMA requests are performed

only when IERRP=0. Moreover the “Error Condi-

tion” interrupt source has a higher priority than the

DMA.

In DMA Not-Suspended mode, the status of

IERRP bit has no effect on DMA requests. Moreo-

ver the DMA has higher priority with respect to oth-

er interrupt sources.

0: DMA Not-Suspended mode

1: DMA Suspended mode

Bit 6:4 = PRL[2:0]

Interrupt/DMA Priority Bits.

The priority is encoded with these three bits. The

value of “0” has the highest priority, the value “7”

has no priority. After the setting of this priority lev-

el, the priorities between the different Interrupt/

DMA sources is hardware defined according with

the following scheme:

– Error condition Interrupt (If DMASTOP=1) (High-

est priority)

– Receiver DMA request

– Transmitter DMA request

– Error Condition Interrupt (If DMASTOP=0

– Data Received/Receiver End Of Block

– Peripheral Ready To Transmit/Transmitter End

Of Block (Lowest priority)

Bit 3 = Reserved.

Must be cleared.

Bit 2 = IERRP

Error Condition pending bit

0: No error

1: Error event detected (if ITE=1)

Note:

Depending

the

status

the

I2CISR.DMASTOP bit, this flag can suspend or

not suspend the DMA requests.

Note: The Interrupt pending bits can be reset by

writing a “0” but is not possible to write a “1”. It is

mandatory to clear the interrupt source by writing a

“0” in the pending bit when executing the interrupt

service routine. When serving an interrupt routine,

the user should reset ONLY the pending bit related

to the served interrupt routine (and not reset the

other pending bits).

To detect the specific error condition that oc-

curred, the flag bits of the I2CSR1 and I2CSR2

Note: The IERRP pending bit is forced high until

the error event flags are set (ADSL and SB flags in

the I2CSR1 register, SCLF, ADDTX, AF, STOPF,

ARLO and BERR flags in the I2CSR2 register). If

at least one flag is set, it is not possible to reset the

IERRP bit.

Bit 1 = IRXP

Data Received pending bit

0: No data received

1: data received (if ITE=1).

Bit 0 = ITXP

Peripheral Ready To Transmit pend-

ing bit

0: Peripheral not ready to transmit

1: Peripheral ready to transmit a data byte (if

ITE=1).

DMASTOP PRL2 PRL1 PRL0

IERRP IRXP ITXP

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