ST92F120JR9T datasheet(236/320 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C INTERFACE (Cont’d)

2C CLOCK CONTROL REGISTER

(I2CCCR)

R243 - Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = FM/SM

Fast/Standard I2C mode.

This bit is used to select between fast and stand-

ard mode. See the description of the following bits.

It is set and cleared by software. It is not cleared

when the peripheral is disabled (I2CCR.PE=0)

Bit 6:0 = CC[6:0]

9-bit divider programming

Implementation of a programmable clock divider.

These bits and the CC[8:7] bits of the I2CECCR

pending on the I

2C mode.

They are not cleared when the interface is disa-

bled (I2CCR.PE=0).

– Standard mode (FM/SM=0): FSCL <= 100kHz

FSCL = INTCLK/(2x([CC8..CC0]+2))

– Fast mode (FM/SM=1): FSCL > 100kHz

FSCL = INTCLK/(3x([CC8..CC0]+2))

Note: The programmed frequency is available

with no load on SCL and SDA pins.

2C OWN ADDRESS REGISTER 1

(I2COAR1)

R244 - Read / Write

Reset Value: 0000 0000 (00h)

7-bit Addressing Mode

Bit 7:1 = ADD[7:1]

Interface address.

These bits define the I

2C bus address of the inter-

face.

They are not cleared when the interface is disa-

bled (I2CCR.PE=0).

Bit 0 = ADD0

Address direction bit.

This bit is don’t care; the interface acknowledges

either 0 or 1.

It is not cleared when the interface is disabled

(I2CCR.PE=0).

Note: Address 01h is always ignored.

10-bit Addressing Mode

Bit 7:0 = ADD[7:0]

Interface address.

These are the least significant bits of the I

2Cbus

address of the interface.

They are not cleared when the interface is disa-

bled (I2CCR.PE=0).

FM/SM

CC6

CC5

CC4

CC3

CC2 CC1 CC0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

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