MPC5200B datasheet(28/72 Pages) FREESCALE

28 / 72 page

MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 13. Timing Diagram—MUXed Mode

1.3.9

ATA

The MPC5200B ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols

using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in

nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds).

ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data

setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the

ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and

ATA drive for different ATA protocols and their respective timing. See the MPC5200B User Manual.

The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in

PIO and Multiword DMA modes.

•

Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that

required by the ATA-4 specification.

•

Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that

required by the ATA-4 specification.

PCI CLK

AD[24:0] (wr)

CSx

R/W

ALE

AD[30:28] (wr)

AD[26:25] (wr)

AD[31,27] (wr)

Address[7:31]

Bank[0:1] bits

TSIZ[0:2] bits

ACK

Data

Data tenure

Address tenure

Data

AD[31:0] (rd)

Data

t13

Address latch

t11

t12

t10

t14

t15

t16

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