MPC5200B datasheet(18/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing

1.3.6.2

Memory Interface Timing-Standard SDRAM Write Command

In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK

clock at the memory device.

Table 19. Standard SDRAM Write Timing

Sym

Description

Min

Max

Units

SpecID

tmem_clk

MEM_CLK period

7.5

—

A5.8

tvalid

Control Signals, Address and MBA Valid

after rising edge of MEM_CLK

—tmem_clk*0.5+0.4

A5.9

thold

Control Signals, Address and MBA Hold after

rising edge of MEM_CLK

tmem_clk*0.5

—

A5.10

DMvalid

DQM valid after rising edge of MEM_CLK

—

tmem_clk*0.25+0.4

A5.11

DMhold

DQM hold after rising edge of Mem_clk

tmem_clk*0.25-0.7

—

A5.12

datavalid

MDQ valid after rising edge of MEM_CLK

—

tmem_clk*0.75+0.4

A5.13

datahold

MDQ hold after rising edge of MEM_CLK

tmem_clk*0.75-0.7

—

A5.14

MEM_CLK

Control Signals

MDQ (Data)

MA (Address)

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Active

NOP

READ

NOP

thold

Row

Column

MBA (Bank Selects)

tvalid

thold

tvalid

thold

tvalid

DQM (Data Mask)

DMvalid

DMhold

NOP

datahold

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