MPC5200B datasheet(17/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt

sources. Take care of interrupt prioritization which may increase the latencies.

Because all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has

to exceed a minimum pulse width of more than one IP_CLK cycle.

NOTES:

1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200B User Manual

for further information.

2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second

interrupt is not recognized at all.

Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt

service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended

to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design

and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.

1.3.6

SDRAM

1.3.6.1

Memory Interface Timing-Standard SDRAM Read Command

Table 17. Minimum Pulse Width for External Interrupts to be Recognized

Name

Min Pulse Width

Max Pulse Width

Reference Clock

SpecID

All external interrupts (IRQs, GPIOs)

> 1 clock cycle

—

IP_CLK

A4.22

Table 18. Standard SDRAM Memory Read Timing

Sym

Description

Min

Max

Units

SpecID

tmem_clk

MEM_CLK period

7.5

—

A5.1

tvalid

Control Signals, Address and MBA Valid after

rising edge of MEM_CLK

—tmem_clk*0.5+0.4

A5.2

thold

Control Signals, Address and MBA Hold after

rising edge of MEM_CLK

tmem_clk*0.5

—

A5.3

DMvalid

DQM valid after rising edge of MEM_CLK

—

tmem_clk*0.25+0.4

A5.4

DMhold

DQM hold after rising edge of MEM_CLK

tmem_clk*0.25-0.7

—

A5.5

datasetup

MDQ setup to rising edge of MEM_CLK

—

0.3

A5.6

datahold

MDQ hold after rising edge of MEM_CLK

0.2

—

A5.7

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