MPC5200B datasheet(42/72 Pages) FREESCALE

部件名	MPC5200B

功能描述	SDRAM / DDR Memory Controller

PDF	72 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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42 / 72 page

MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 32. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)

NOTE

Output timing is specified at a nominal 50 pF load.

Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)

Sym

Description

Min

Max

Units

SpecID

Cycle time

1024

IP-Bus Cycle(1)

1 Inter Peripheral Clock is defined in the MPC5200B User Manual.

A11.12

Clock high or low time

512

IP-Bus Cycle(1)

A11.13

Slave select to clock delay

15.0

—

A11.14

Output Data valid after Slave Select (SS)

—

50.0

A11.15

Output Data valid after SCK

—

50.0

A11.16

Input Data setup time

50.0

—

A11.17

Input Data hold time

0.0

—

A11.18

Slave disable lag time

15.0

—

A11.19

Sequential Transfer delay

—

IP-Bus Cycle(1)

A11.20

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Output

MISO

Input

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