MPC5200B datasheet(47/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

1.3.16

PSC

1.3.16.1

Codec Mode (8,16,24 and 32-bit)/I2S Mode

NOTE

Output timing is specified at a nominal 50 pF load.

Figure 37. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Master Mode

Table 42. Timing Specifications—8,16, 24, and 32-bit CODEC / I2S Master Mode

Sym

Description

Min

Typ

Max

Units

SpecID

Bit Clock cycle time, programmed in CCS register

40.0

—

A15.1

Clock duty cycle

—

%(1)

1 Bit Clock cycle time

A15.2

Bit Clock fall time

—

7.9

A15.3

Bit Clock rise time

—

7.9

A15.4

FrameSync valid after clock edge

—

8.4

A15.5

FrameSync invalid after clock edge

—

8.4

A15.6

Output Data valid after clock edge

—

9.3

A15.7

Input Data setup time

6.0

—

A15.8

BitClk

(CLKPOL=0)

BitClk

(CLKPOL=1)

FrameSync

(SyncPol = 1)

TxD

Output

FrameSync

(SyncPol = 0)

Output

RxD

Input

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