MPC5200B datasheet(12/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

1.3

AC Electrical Characteristics

Hyperlinks to the indicated timing specification sections are provided below.

1.3.1

AC Test Timing Conditions:

Unless otherwise noted, all test conditions are as follows:

•

TA = -40 to 85 oC

•

Tj = -40 to 115 oC

•

VDD_CORE = 1.42 to 1.58 V

VDD_IO = 3.0 to 3.6 V

Table 11. e300 PLL Specifications

Characteristic

Sym

Notes

Min

Typical

Max

Unit

SpecID

e300 frequency

fcore

(1)

1 The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system

frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or

minimum operating frequencies in Table 12.

—

550

MHz

O4.1

e300 cycle time

tcore

(1)

2.85

—

40.0

O4.2

e300 VCO frequency

fVCOcore

(1)

400

—

1200

MHz

O4.3

e300 input clock frequency

fXLB_CLK

—

367

MHz

O4.4

e300 input clock cycle time

tXLB_CLK

2.73

—

50.0

O4.5

e300 input clock jitter

tjitter

(2)

2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different

types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.

Systemic jitter is passed into and through the PLL to the internal clock circuitry.

—

150

O4.6

e300 PLL relock time

tlock

(3)

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required

for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

—

100

μsO4.7

•

AC Operating Frequency Data

•

USB

•

Clock AC Specifications

•

SPI

•Resets

•

MSCAN

•

External Interrupts

•

I2C

•

SDRAM

•

J1850

•PCI

•PSC

•

Local Plus Bus

•

GPIOs and Timers

•

ATA

•

IEEE 1149.1 (JTAG) AC Specifications

•

Ethernet

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