MPC5200B datasheet(50/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 40. Timing Diagram — IrDA Transmit Line

1.3.16.4

SPI Mode

NOTE

Output timing is specified at a nominal 50 pF load.

Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A15.26

SCK pulse width, 50% SCK duty cycle

15.0

—

A15.27

Slave select clock delay, programable in the PSC CCS register

30.0

—

A15.28

Output Data valid after Slave Select (SS)

—

8.9

A15.29

Output Data valid after SCK

—

8.9

A15.30

Input Data setup time

6.0

—

A15.31

Input Data hold time

1.0

—

A15.32

Slave disable lag time

—

8.9

A15.33

Sequential Transfer delay, programable in the PSC CTUR / CTLR

15.0

—

A15.34

Clock falling time

—

7.9

A15.35

Clock rising time

—

7.9

A15.36

IrDA_TX

(SIR / FIR / MIR)

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