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MPC5200B 数据表(PDF) 48 Page - Freescale Semiconductor, Inc

部件名 MPC5200B
功能描述  SDRAM / DDR Memory Controller
PDF  72 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC5200B 数据表(HTML) 48 Page - Freescale Semiconductor, Inc

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MPC5200B Data Sheet, Rev. 3
48
Freescale Semiconductor
NOTE
Output timing is specified at a nominal 50 pF load.
Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Slave Mode
Table 43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I2S Slave Mode
Sym
Description
Min
Typ
Max
Units
SpecID
1
Bit Clock cycle time
40.0
—
—
ns
A15.9
2
Clock duty cycle
—
50
—
%(1)
1
Bit Clock cycle time
A15.10
3
FrameSync setup time
1.0
—
—
ns
A15.11
4
Output Data valid after clock edge
—
—
14.0
ns
A15.12
5
Input Data setup time
1.0
—
—
ns
A15.13
6
Input Data hold time
1.0
—
—
ns
A15.14
BitClk
3
(CLKPOL=0)
BitClk
(CLKPOL=1)
FrameSync
(SyncPol = 1)
TxD
Output
Input
Input
4
5
Input
FrameSync
(SyncPol = 0)
Input
RxD
Input
1
22
6



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