MPC5200B datasheet(43/72 Pages) FREESCALE

部件名	MPC5200B

功能描述	SDRAM / DDR Memory Controller

PDF	72 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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43 / 72 page

MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)

NOTE

Output timing is specified at a nominal 50 pF load.

Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)

Sym

Description

Min

Max

Units

SpecID

Cycle time

1024

IP-Bus Cycle(1)

1 Inter Peripheral Clock is defined in the MPC5200B User Manual.

A11.21

Clock high or low time

512

IP-Bus Cycle(1)

A11.22

Slave select to clock delay

15.0

—

A11.23

Output data valid

—

20.0

A11.24

Input Data setup time

20.0

—

A11.25

Input Data hold time

20.0

—

A11.26

Slave disable lag time

15.0

—

A11.27

Sequential Transfer delay

—

IP-Bus Cycle(1)

A11.28

Clock falling time

—

7.9

A11.29

Clock rising time

—

7.9

A11.30

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Input

MISO

Output

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