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MPC5200B 数据表(PDF) 49 Page - Freescale Semiconductor, Inc

部件名 MPC5200B
功能描述  SDRAM / DDR Memory Controller
PDF  72 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC5200B 数据表(HTML) 49 Page - Freescale Semiconductor, Inc

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MPC5200B Data Sheet, Rev. 3
Freescale Semiconductor
49
1.3.16.2
AC97 Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Figure 39. Timing Diagram — AC97 Mode
1.3.16.3
IrDA Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 44. Timing Specifications — AC97 Mode
Sym
Description
Min
Typ
Max
Units
SpecID
1
Bit Clock cycle time
81.4
ns
A15.15
2
Clock pulse high time
40.7
ns
A15.16
3
Clock pulse low time
40.7
ns
A15.17
4
FrameSync valid after rising clock edge
13.0
ns
A15.18
5
Output Data valid after rising clock edge
14.0
ns
A15.19
6
Input Data setup time
1.0
ns
A15.20
7
Input Data hold time
1.0
ns
A15.21
Table 45. Timing Specifications — IrDA Transmit Line
Sym
Description
Min
Max
Units
SpecID
1
Pulse high time, defined in the IrDA protocol definition
0.125
10000
μs
A15.22
2
Pulse low time, defined in the IrDA protocol definition
0.125
10000
μs
A15.23
3
Transmitter rising time
7.9
ns
A15.24
4
Transmitter falling time
7.9
ns
A15.25
BitClk
(CLKPOL=0)
FrameSync
(SyncPol = 1)
Sdata_out
Output
Input
6
Output
Sdata_in
Input
1
4
3
5
2
7



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