MPC5200B datasheet(20/72 Pages) FREESCALE

部件名	MPC5200B

功能描述	SDRAM / DDR Memory Controller

PDF	72 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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20 / 72 page

MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing

MEM_CLK

Control Signals

MDQ (Data)

MA (Address)

MEM_CLK

MDQS (Data Strobe)

NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Active

NOP

READ

NOP

thold

Row

Column

MBA (Bank Selects)

tvalid

thold

tvalid

thold

tvalid

tdata_valid_min

tdata_valid_max

Read Data

tdata_sample_min

tdata_sample_max

Sample Window

MDQ (Data)

MDQS (Data Strobe)

tdata_valid_min

tdata_valid_max

Read Data

tdata_sample_min

tdata_sample_max

Sample Window

Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data

Sample

position

Sample

position

Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signal

0.5 * tMEM_CLK

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