MPC5200B datasheet(41/72 Pages) FREESCALE

部件名	MPC5200B

功能描述	SDRAM / DDR Memory Controller

PDF	72 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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41 / 72 page

MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 31. Timing Diagram—USB Output Line

1.3.12

SPI

NOTE

Output timing is specified at a nominal 50 pF load.

Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)

Sym

Description

Min

Max

Units

SpecID

Cycle time

1024

IP-Bus Cycle(1)

1 Inter Peripheral Clock is defined in the MPC5200B User Manual.

A11.1

Clock high or low time

512

IP-Bus Cycle(1)

A11.2

Slave select to clock delay

15.0

—

A11.3

Output Data valid after Slave Select (SS)

—

20.0

A11.4

Output Data valid after SCK

—

20.0

A11.5

Input Data setup time

20.0

—

A11.6

Input Data hold time

20.0

—

A11.7

Slave disable lag time

15.0

—

A11.8

Sequential transfer delay

—

IP-Bus Cycle(1)

A11.9

Clock falling time

—

7.9

A11.10

Clock rising time

—

7.9

A11.11

USB_OE

USB_TXN

USB_TXP

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