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MPC5200B 数据表(PDF) 29 Page - Freescale Semiconductor, Inc

部件名 MPC5200B
功能描述  SDRAM / DDR Memory Controller
PDF  72 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC5200B 数据表(HTML) 29 Page - Freescale Semiconductor, Inc

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MPC5200B Data Sheet, Rev. 3
Freescale Semiconductor
29
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
•
The MPC5200B operating frequency (IP bus clock frequency)
•
Internal MPC5200B bus latencies
•
Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User Manual.
NOTE
All output timing numbers are specified for nominal 50 pF loads.
Table 27. PIO Mode Timing Specifications
Sym
PIO Timing Parameter
Min/Max
(ns)
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
SpecID
t0
Cycle Time
min
600
383
240
180
120
A8.1
t1
Address valid to DIOR/DIOW setup
min
70
50
30
30
25
A8.2
t2
DIOR/DIOW pulse width 16-bit
8-bit
min
min
165
290
125
290
100
290
80
80
70
70
A8.3
t2i
DIOR/DIOW recovery time
min
—
—
—
70
25
A8.4
t3
DIOW data setup
min
60
45
30
30
20
A8.5
t4
DIOW data hold
min
30
20
15
10
10
A8.6
t5
DIOR data setup
min
50
35
20
20
20
A8.7
t6
DIOR data hold
min
55555
A8.8
t9
DIOR/DIOW to address
valid hold
min
2015101010
A8.9
tA
IORDY setup
max
35
35
35
35
35
A8.10
tB
IORDY pulse width
max
1250
1250
1250
1250
1250
A8.11



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