R8CSLASH2G datasheet(167/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 147 of 318

REJ09B0387-0100

Figure 17.3

Registers TRAMR, TRAPRE, and TRA

Timer RA Mode Register(1)

Symbol

Address

After Reset

TRAMR

0102h

00h

Bit Symbol

Bit Name

Function

NOTE:

TCKCUT

TCK1

b3 b2

—

(b3)

b1 b0

Timer RA count source

select bits

b6 b5 b4

0 0 0 : f1

0 0 1 : f8

0 1 0 : fOCO

0 1 1 : f2

1 0 0 : fC32

1 0 1 :

1 1 0 :

Do not set.

1 1 1 :

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

b7 b6 b5 b4

TMOD1

TMOD0

Timer RA operating mode

select bits

b2 b1 b0

0 0 0 : Timer mode

0 0 1 : Pulse output mode

0 1 0 : Event counter mode

0 1 1 : Pulse w idth measurement mode

1 0 0 : Pulse period measurement mode

1 0 1 :

1 1 0 :

Do not set.

1 1 1 :

TMOD2

—

TCK0

When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.

Timer RA count source

cutoff bit

0 : Provides count source

1 : Cuts off count source

TCK2

Timer RA Prescaler Register

Symbol

Address

After Reset

TRAPRE

0103h

FFh(1)

Mode

Function

Setting Range

NOTE:

Pulse w idth

measurement mode

Timer mode

Counts an internal count source

00h to FFh

Pulse output mode

Counts an internal count source

00h to FFh

Counts internal count source

When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.

Event counter mode

Counts an external count source

00h to FFh

Pulse period

measurement mode

00h to FFh

Timer RA Register

Symbol

Address

After Reset

TRA

0104h

FFh(1)

Mode

Function

Setting Range

NOTE:

00h to FFh

When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.

All modes

Counts on underflow of timer RA prescaler

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