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R8C/2G 数据表(PDF) 208 Page - Renesas Technology Corp |
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R8C/2G 数据表(HTML) 208 Page - Renesas Technology Corp |
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208 / 344 page  R8C/2G Group 17. Timers Rev.1.00 Apr 04, 2008 Page 188 of 318 REJ09B0387-0100 Figure 17.33 TRECR2 Register in Real-Time Clock Mode Table 17.12 Interrupt Sources Factor Interrupt Source Interrupt Enable Bit Periodic interrupt triggered every week Value in TREWK register is set to 000b (Sunday) (1-week period) WKIE Periodic interrupt triggered every day TREWK register is updated (1-day period) DYIE Periodic interrupt triggered every hour TREHR register is updated (1-hour period) HRIE Periodic interrupt triggered every minute TREMIN register is updated (1-minute period) MNIE Periodic interrupt triggered every second TRESEC register is updated (1-second period) SEIE Timer RE Control Register 2 Symbol Address After Reset TRECR2 011Dh 00XXXXXXb Bit Symbol Bit Name Function RW NOTE: 1. b3 b2 DYIE b1 b0 SEIE b7 b6 b5 b4 0 RW MNIE RW Periodic interrupt triggered every minute enable bit(1) 0 : Disable periodic interrupt triggered every minute 1 : Enable periodic interrupt triggered every minute Periodic interrupt triggered every second enable bit(1) 0 : Disable periodic interrupt triggered every second 1 : Enable periodic interrupt triggered every second Periodic interrupt triggered every hour enable bit(1) 0 : Disable periodic interrupt triggered every hour 1 : Enable periodic interrupt triggered every hour Do not set multiple enable bits to 1 (enable interrupt). HRIE RW RW Periodic interrupt triggered every day enable bit(1) 0 : Disable periodic interrupt triggered every day 1 : Enable periodic interrupt triggered every day COMIE Compare match interrupt enable bit RW RW — (b7-b6) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Set to 0 in real-time clock mode. WKIE Periodic interrupt triggered every w eek enable bit(1) 0 : Disable periodic interrupt triggered every w eek 1 : Enable periodic interrupt triggered every w eek |
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